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Latest posts
Last updated about 5 hours ago
From Tokens To Tasks: Why Agentic AI Changes The Infrastructure Conversation
about 6 hours ago
At 8:42 a.m., a developer opens her laptop to a red build...
Linear Optics And The Push To Scale AI Interconnects
about 6 hours ago
AI clusters keep getting larger and more demanding. Training a trillion-parameter model...
What Will It Take To Deploy CPO At Scale?
about 6 hours ago
Co-packaged optics (CPO) is at an inflection point. We see it rapidly...
Is Pergrammable A Word?
about 6 hours ago
The price tag to invest in bespoke silicon for devices such as...
Packet-Based NPUs In The LLM Era: From Compute-Bound CNNs To Memory-Bound Edge And Automotive Workloads
about 6 hours ago
Many Semiconductor Engineering readers know the basic story behind Expedera’s Origin NPU...
What Self-Verifying Means In Agentic EDA Workflows And Why It Matters
about 6 hours ago
Last month, we covered the architectural decisions behind a production-ready EDA AI...
DDR5 9600 RDIMMs: Raising The Performance Benchmark For Server Memory
about 6 hours ago
The rapid evolution of AI, high-performance computing (HPC) and cloud infrastructure is...
Copper’s Grip On AI Scaling Is Starting To Slip
about 6 hours ago
Key Takeaways: Scale-up may go beyond one rack and may use optical...
Vertical Integration Becoming Pervasive
about 6 hours ago
Key Takeaways Hardware and software development has traditionally been disconnected, creating little...
The 1-Megawatt Rack Debate
about 6 hours ago
Key Takeaways The push toward 1-megawatt racks is forcing fundamental changes in...
Self-Supervised Layout Generation To Fix Advanced-Node DRVs (Nvidia, Duke)
about 14 hours ago
Researchers from NVIDIA and Duke University published a technical paper titled “SCALE...
Defect Prediction in Optical Lithography, EUVL, and NIL (National Taiwan University)
about 19 hours ago
National Taiwan University researchers published a technical paper titled “From Lithography to...